Application Engineering, Sr Engineer

As a Senior Applications Engineer at Synopsys, you will collaborate with customers to understand their verification challenges and provide tailored technical solutions using Synopsys Verification Platform. You will support customer projects throughout their tapeout schedules, ensure timely resolution of technical issues, and deliver technical presentations, workshops, and training sessions on Synopsys EDA tools, methodologies, and best practices.

Requirements

• Master’s degree in Electronics, or Bachelor’s degree in Electronics with 1-2 years of relevant experience
• Solid understanding of digital design, HDLs (Verilog, VHDL), and System Verilog
• Experience with dynamic simulation verification, including methodologies, debug, low power, and coverage
• Familiarity with Synopsys EDA tools (VCS, Verdi) is a plus
• Proficiency in UNIX environments and scripting languages such as Tcl, with the ability to automate and optimize workflows
• Excellent written and verbal communication skills, with experience interfacing directly with clients

Benefits

• Comprehensive range of health, wellness, and financial benefits