ASIC Verification, Principal Engineer

We are seeking an experienced ASIC Digital Verification Engineer to join our team at Synopsys. The successful candidate will design, implement and optimize verification environments to ensure the correctness of Interface IP protocols. They will collaborate with design and architecture teams, perform functional coverage analysis and drive coverage closure. The candidate will also mentor and guide junior verification engineers in best practices and methodologies.

Requirements

• Extensive experience in ASIC digital verification
• Proficiency in System Verilog, SVA and UVM methodologies
• Strong understanding of digital design and verification concepts
• Familiarity with wider digital ASIC and IP development flow
• Experience with simulation tools such as VCS, Model Sim, or similar
• Strong analytical and problem-solving skills
• Excellent communication skills