Senior FPGA Verification Engineer
Ursa MajorColorado, United States
Posted January 7, 2026
120000 - 150000 USD year
Full Time
About the Company
Ursa Major is a company that designs and delivers propulsion and defense systems for the aerospace and defense industry.
Job Description
Join Ursa Major as a Senior FPGA Verification Engineer and be an integral part of the Avionics development team. Architect, develop and execute test benches, verify requirements, collect functional and code coverage metrics, and prepare design review materials.
Requirements
- 5+ years' experience with SystemVerilog Universal Verification Methodology (UVM), Pyuvm or similar verification methodology
- Experience with COCOTB and python-based HDL simulations
- Experienced in running ASIC/FPGA simulations using QuestaSim, VCS, Riviero-Pro, or Verilator
- Experienced in collecting ASIC/FPGA coverage metrics
- Experienced in defining test plans, generating test cases and testbench components
- Experienced in writing VHDL, Verilog or SystemVerilog code for ASIC/FPGA design
- Experience in Python scripting, simulations and tool development
Benefits
- Unlimited PTO - Vacation, Sick, Personal, and Bereavement
- Paid Parental and Adoptive Leave
- Medical, Dental and Vision Insurance
- Tax Advantage Accounts (HSA/FSA)
- Employer Paid Short and Long Term Disability, Basic Life, AD&D
- Additional Benefit Options Including Voluntary Life and Emergency Medical Transport
- EAP Program
- Retirement Savings Plan - Traditional 401(k) and a Roth 401(k)
- Equity Grants in the Company
