RTL DESIGN ENGINEER

Apply now to become an RTL DESIGN ENGINEER at Wipro Limited, responsible for designing and verifying digital logic circuits and integrating SOC RTL. Must have 2+ years of experience in IC design flow and methodology, proficiency in Verilog/SystemVerilog, and programming skills in C/C++ and Perl/Shell script.

Requirements

• 2+ years of experience in IC design flow and methodology
• Proficiency in Verilog/SystemVerilog
• Proficiency in programming skills in C/C++ and Perl/Shell script
• Design specification determination and circuit implementation capability
• Understanding of IC design flow and methodology

Benefits

• Competitive salary
• Opportunities for growth and development
• Collaborative and dynamic work environment