Design Verification Engineer

This Design Verification Engineer role is responsible for ensuring bug-free first silicon for a part of the SoC / IP. The role involves developing detailed test and coverage plans based on the micro-architecture, developing verification methodology, and improving verification infrastructure and efficiency. The role also requires working with LLMs and related technologies.

Requirements

• BS degree in technical subject area
• Minimum 3 years of proven experience or equivalent
• Strong knowledge of OOP, SystemVerilog and UVM
• Strong knowledge in developing scalable and portable test-benches
• Experience with verification methodologies and tools
• Some working experience using LLMs for efficiency and quality