Emulation Verification Engineer

Join the Emulation verification team to use Emulation for verification of large SoCs. The role involves porting designs onto the Palladium platform, completing detailed Emulation testplans, collaborating with various teams, developing monitors/checkers, stimulus, performing low power testing, and developing random stimulus infrastructure using Verilog/System Verilog/UVM.

Requirements

• BS + 3 years relevant industry experience
• Understanding of the tool flow from RTL to Emulation
• Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow
• Proven design verification skills
• Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions
• Experience with System Verilog verification environments including C/C++ DPI, UVM
• Experience with writing and debugging test FW
• Experience on any Scripting (Perl/Python/TCL)
• Excellent analytical and debug skills

Benefits

• Apple is an equal opportunity employer that is committed to inclusion and diversity.