Design Verification Engineer

This Design Verification Engineer role focuses on ensuring bug-free first silicon for a SoC / IP component. The role involves developing verification methodologies, executing verification plans, and using LLMs for efficient execution and improved quality. It requires developing verification environment and understanding design specification.

Requirements

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions
• Use LLMs to verify efficiently
• Minimize qualifications: BS degree in technical subject area and 10+ years relevant industry experience
• Preferred qualifications: Deep knowledge of OOP, SystemVerilog and UVM, strong experience with verification methodologies, and using LLMs

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Tuition reimbursement
• Discretionary bonuses
• Relocation