SoC Physical Design Engineer, STA/Timing

This position involves working with design teams to understand and resolve timing constraints, primarily through TCL scripting and analysis. The role focuses on creating and maintaining timing infrastructure, documentation, and analysis methodologies for project tapeouts. Key responsibilities include identifying timing issues, implementing timing solutions, and adhering to best practices.

Requirements

• BS degree
• 10+ years of relevant industry experience
• Strong programming skills with TCL
• Knowledge of noise, crosstalk, OCV, and other timing modeling effects
• Understanding of circuit modeling including timing models, worst-case timing corner selection, and SPICE simulation
• Experience with ECO techniques and implementation
• Experience with scripting languages such as Perl or Python