STA engineer

The STA Engineer will develop and support automated signoff flows, focusing on Full Chip Timing/Noise convergence and signoff for high-quality TO. Responsibilities include hierarchical Timing flows, power optimizations, block-level budget generation, custom IP integration, and close collaboration with Design, DFT, architecture, and Power teams.

Requirements

• 4+ years experience in Static Timing analysis
• Extensive experience with one of the commercial STA tools
• Familiarity with hierarchical design approach, top-down design, timing and physical convergence
• Experience with backend STA closure and Signoff
• Deep understanding of designs' constraints development
• Good understanding of AC timing from specs to implementation
• Good understanding of DFT modes and their constraints
• Good communication skills and team player
• Quick learning of flows and methods