STA Engineer

Astera Labs is seeking a visionary Tech Lead STA Engineer to help build its local engineering powerhouse in Israel. The role involves taking full ownership of the STA flow and sign-off methodologies, establishing rigorous criteria for success in demanding data center environments.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• 5+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies
• Deep expertise in multi-scenario STA, timing/SDC constraint development and verification
• Experience working on advanced process technologies (7nm and below)
• Solid understanding of advanced margining methodologies including OCV, AOCV, and POCV
• Strong knowledge of physical design flows (P&R, Physical Verification) and their intersection with timing closure

Benefits

• Opportunity to work on cutting-edge semiconductor solutions
• Chance to shape the timing methodology for AI infrastructure connectivity
• Collaborative and dynamic work environment