Timing Design Engineer

Timing Design Engineer responsible for timing sign-off, STA and sign-off flow development, and ownership of IP and block level timing constraints.

Requirements

• BS degree in technical discipline
• 10+ years of relevant experience
• Proven knowledge of ASIC design timing closure flow and methodology
• 2+ years of experience in writing ASIC timing constraints and timing closure
• Expertise in STA tools (Primetime) and flow
• Knowledge of timing corners/modes, process variations and signal integrity related issues
• Hands on experience in timing/SDC constraints generation and management
• Proficient in scripting languages (Tcl and Perl)
• Familiarity with synthesis, DFT and backend related methodology and tools
• Strong communication skills

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan
• Visa Sponsorship
• Four Day Work Week
• Generous Parental Leave
• Tuition Reimbursement
• Relocation Assistance