Timing Design Engineer

Join Apple as a Timing Design Engineer and be part of a team that commits to values that lead to great work. As an ASIC STA Engineer, responsibilities will include timing sign-off, STA and sign-off flow development, and ownership of IP and block level timing constraints.

Requirements

• BS degree in technical discipline
• 3+ years of relevant experience
• Proven knowledge of ASIC design timing closure flow and methodology
• Expertise in STA tools (Primetime) and flow
• Knowledge of timing corners/modes, process variations and signal integrity related issues
• Hands on experience in timing/SDC constraints generation and management
• Proficient in scripting languages (Tcl and Perl)
• Familiarity with synthesis, DFT and backend related methodology and tools
• Strong communication skills

Benefits

• 401k Matching
• Generous Paid Time Off
• Healthcare Services
• Retirement Plan