Timing Design Engineer

We're seeking a Timing Design Engineer to join our team. As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints, and closely interacting with RTL designer, CAD, and Physical design team to achieve sign-off quality timing constraints.

Requirements

• BS degree in technical discipline with minimum 10 years of relevant experience.
• Proven knowledge of the ASIC design timing closure flow and methodology.
• 2+ years of experience in writing ASIC timing constraints and timing closure.
• Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues.
• Hands on experience in timing/SDC constraints generation and management.
• Proficient in scripting languages (Tcl and Perl).
• Familiarity with synthesis, DFT and backend related methodology and tools.
• Strong communication skills are a pre-requisite – you will be collaborating with many diverse groups at Apple.

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan
• Visa Sponsorship
• Four Day Work Week
• Generous Parental Leave
• Tuition Reimbursement
• Relocation Assistance