Digital IC Backend Design Engineer

Arago is developing a processor that harnesses the unique physical properties of light to address both memory and computational limitations. We're looking for a Digital Backend Design Engineer to execute full-chip and block-level physical design tasks, develop and optimize the digital backend flow, and drive timing closure, power optimization, and physical verification.

Requirements

• Master's or PhD degree in Electrical/Electronic Engineering or a related field.
• 4+ years experience in digital IC backend implementation.
• Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.
• Strong understanding of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.
• Experience with advanced technology nodes (22nm or below preferred).
• Familiarity with the GF22 FDX+ process is highly advantageous.
• Skilled in Tcl scripting for automation of backend flows.
• Experience in hierarchical or full-chip implementation is preferred.

Benefits

• Competitive cash compensation that reflects your expertise and experience.
• Stock options.
• Ownership of a key technical area.
• Being part of the early stage of one of the hottest AI startups (currently in stealth mode).
• A fun, dynamic, and multicultural team in a collaborative environment.
• Exciting professional growth opportunities.