Senior Engineer (Level 2)

Senior Engineer (Level 2) responsible for FPGA/ASIC design cycle, development, simulation, test & debug, verification & validation for Embedded Data acquisitions applications.

Requirements

• Familiarity with FPGA/ASIC design cycle
• Experience with Verilog, VHDL, System Verilog programming languages
• 4 year degree and a minimum of 5 years of related experience
• or an advanced degree without experience
• or equivalent work experience