Principal Physical Design Engineer

Astera Labs is seeking a Principal Physical Design Engineer to contribute to the development and refinement of rack-scale AI infrastructure. The role involves collaborating with hyperscalers and partners to integrate semiconductor-based technologies with COSMOS software, enabling scalable and flexible connectivity solutions. The company emphasizes collaboration, innovation, and a customer-centric approach.

Requirements

• Strong academic and technical background in electrical engineering.
• Bachelor’s degree in EE / Computer required, Master’s degree preferred.
• ≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Hands-on knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and backend tools.
• Full chip or block level ownership from architecture to GDSII.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity with System Verilog/Verilog
• Experience with DFT tools and techniques.
• Experience with IP vendors for both RTL and hard-mac blocks.
• Good scripting skills in python or Perl
• Basic knowledge of design for test (DFT)
• Good scripting skills in python or Perl

Benefits

• Competitive salary
• Opportunity for growth
• Collaborative work environment