Senior Physical Design Engineer

Astera Labs is seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node.

Requirements

• Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm.
• Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power.
• Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis.
• Handle advanced physical design topics: EM/IR analysis and power grid optimization, Congestion analysis and mitigation, Clock domain crossing and skew optimization, RC extraction-aware placement and routing.
• Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.
• Participate in defining floorplan strategy and chip partitioning for multi-gigabit transceivers.
• Perform ECO implementation and support tapeout signoff activities.
• Ensure DRC/LVS/ANT/CELL/ERC clean database using industry-standard physical verification tools.
• Use industry-standard tools (e.g., ICC2, Innovus, Voltus, RedHawk, Calibre) for implementation and signoff.
• Develop and maintain automation scripts (Tcl, Python, Perl) for physical design flows and regressions.

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan
• Visa Sponsorship
• Four Day Work Week
• Generous Parental Leave
• Tuition Reimbursement
• Relocation Assistance