Senior/Staff Physical Design Engineer

As a Senior/Staff Physical Design Engineer at Astera Labs, you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs. You will work closely with designers, verification engineering, and engineering operations to accomplish this task.

Requirements

• Strong academic and technical background in electrical engineering
• 3+ years' experience supporting or developing complex SoC/silicon products
• Professional attitude with ability to prioritize tasks, plan customer meetings, and work with minimal guidance
• Hands-on knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification, and other backend tools and methodologies
• Block level ownership from architecture to GDSII, driving multiple complex designs to production
• Experience with Cadence and/or Synopsys physical design tools/flows
• Familiarity with System Verilog/Verilog and proven expertise in developing/maintaining timing constraints
• Experience with DFT tools and techniques, and working with IP vendors

Benefits

• Base salary range: $135,000 - $165,000 (Senior Level), $160,000 - $195,000 (Staff Level)
• Opportunity to work with a diverse team and contribute to the company's mission