Astera Labs is seeking a Sr. Principal DSP Architect to lead the definition and development of next-generation Digital Signal Processing (DSP) architectures for high-speed PAM4 systems and coherent/direct-detect optical transceivers. The role involves bridging theoretical communications theory and silicon implementation, driving the roadmap for 800G, 1.6T, and beyond.
Requirements
- PhD or MS in Electrical Engineering, Communication Theory, or a related field
- 12+ years of experience in DSP design, specifically for high-speed SerDes or optical communications
- Expertise in PAM4 signaling and associated challenges
- Deep understanding of Digital Filter Design (FIR, IIR) and adaptive signal processing
- Experience with high-speed ADC/DAC architectures and their impact on DSP performance
Benefits
- Generous Paid Time Off
- 401k Matching
- Retirement Plan
- Four Day Work Week
- Generous Parental Leave
- Tuition Reimbursement
- Relocation Assistance