Staff ASIC Design Engineer

Axiado is seeking a Staff ASIC Design Engineer to develop the design and implementation/integration of SoCs, with 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization.

Requirements

• 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization
• Proficient in writing clear, implementable micro-architecture specifications
• Expertise in writing efficient RTL code in Verilog and SoC integration
• Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure
• Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce
• Fluency with scripting languages (e.g., Perl, Python)
• Must have gone through at least one complete tape-out cycle