Design Verification Engineer

The CSG group at Broadcom is seeking a Design Verification Engineer to develop and execute verification environments for cutting-edge network switch routing designs.

Requirements

• MSEE or BSEE or equivalent, with concentration in digital design and excellent academic standing.
• Familiar with Hardware description languages (Verilog/SystemVerilog/UVM), scripting languages (Perl, Python) and Object Oriented Programming (OOP).
• Exposure to cutting edge verification and validation techniques and methodologies using Object Oriented modular reusable environments in languages such as Systemverilog, Perl, Python.
• Strong understand and prior experience of end-to-end verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production.
• Excellent verbal and written communication skills.

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave
• vacation time
• Paid Family Leave