Design Verification Engineer

As a Design Verification Engineer, you will be responsible for verifying SoC & Ethernet IPs for leading edge Ethernet Switch products, working with design, integration, and IP teams.

Requirements

• B. Tech. with 8 years of experience or M. Tech. with 6 years of experience
• Expertise in System Verilog and UVM methodology
• Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in development of System Verilog/UVM based verification environments from scratch is a plus
• Experience with IP verification for protocols like AMBA/ ARM CPU cores/PCIe/DDR/ USB/ Ethernet/ Security
• Highly motivated individual with strong debugging and analytical skills

Benefits

• Equal opportunity employer
• Pregnancy and medical condition protection
• Protected veteran status protection