Physical Design Timing Engineer (STA)

The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer engineering
• A minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools
• Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints
• Well versed with scripting languages like TCL and Python, PERL, or Shell
• Strong problem solving skills with attention to every technical aspect
• Be a strong team player with clear and precise communication skills

Benefits

• Medical
• Dental
• Vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence