Senior ASIC Design Engineer

Senior ASIC Design Engineer position available at BTA Design Services. Develop synthesis and timing constraints for complex logic blocks and sub-systems, design and implement complex RTL logic, and interface with verification team and design team.

Requirements

• A minimum of 8 years of relevant experience in ASIC design.
• Experience with modern day ASIC development including complex RTL logic design, synthesis, STA, lint, LEC, and understanding of PnR.
• Experience developing synthesis and timing constraints for complex logic blocks and sub-systems on large, timing critical digital designs.
• Experience in a lab environment, troubleshooting issues up to the system level.
• Experience or knowledge in one or more of the following: ARM A** or RISC-V Application Processor Sub-Systems, Processor Fabric Interfaces (ARM preferred, coherent and non-coherent), Caches, Non-Volatile memory, DSP Cores, AI Acceleration Cores, Networking Switch/Router Datapaths, Packet Processing, OTN, Ethernet.
• Experience with one or more industry standard interfaces e.g. 10/25/40/100Gb Ethernet and OTN, PCIe, SPI, I2C, USB, AXI, AHB, AMBA, GPIO, SRIO, DDR/SDRAM/DMA, NV Memories
• Test verification and scripting experience is a must.
• Track record as a self-starter, a team player and a leader.

Benefits

• Company bonus
• Benefits plan