Lead Application Engineer – Digital Verification

Lead Application Engineer for Digital Verification, responsible for leading and supporting digital verification solutions, working closely with sales team, and engaging with customers to ensure successful adoption and deployment of Cadence verification technologies.

Requirements

• Bachelor's degree or higher in Computer Science, Electrical Engineering, or a related field
• 5–10 years of relevant industry experience
• 5–10 years of hands-on experience and strong expertise in hardware design and/or verification methodologies
• Solid hands-on verification experience using UVM, SystemVerilog, Verilog, VHDL, SystemC, and SystemVerilog Assertions (SVA)
• Hands-on experience with Cadence Verification IP or Jasper is a strong plus
• Good understanding of code coverage and functional coverage concepts, tools, and technologies
• Strong communication skills in English