Lead Application Engineer – Digital Verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We're looking for a Lead Application Engineer to lead and support our digital verification solution for customer projects or pre-sales engagements.

Requirements

• Bachelor’s degree or higher in Computer Science, Electrical Engineering, or a related field
• 5–10 years of relevant industry experience
• 5–10 years of hands‐on experience and strong expertise in hardware design and/or verification methodologies
• Solid hands‐on verification experience using UVM, SystemVerilog, Verilog, VHDL, SystemC, and SystemVerilog Assertions (SVA)
• Hands‐on experience with Cadence Verification IP or Jasper is a strong plus
• Good understanding of code coverage and functional coverage concepts, tools, and technologies
• Strong communication skills in English, with the ability and motivation to work in a global, customer‐facing environment with customers and internal business unit teams
• Valid passport with no travel restrictions; willingness to travel as required

Benefits

• 401k Matching
• Generous Paid Time Off
• Retirement Plan
• Relocation Assistance
• Tuition Reimbursement