Lead Design Engineer - Verification
Cadence Design SystemsShanghai, China
Posted December 16, 2025
Full Time
About the Company
Cadence hires and develops leaders and innovators who want to make an impact on the world of technology.
Job Description
Lead Design Engineer - Verification at Cadence in Shanghai. Seeking a skilled VLSI Design Verification Engineer with 3–5 years of experience to join the team supporting SOC design projects for leading customers.
Requirements
- Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field with 3–5 years of experience in VLSI/SOC design verification
- Strong expertise in System Verilog, UVM, and Verification tools