Lead Design Engineer - Verification
Cadence Design SystemsShanghai, China
Posted December 16, 2025
Full Time
About the Company
Cadence Design Systems specializes in electronic systems design for innovative market applications.
Job Description
Lead Design Engineer - Verification at Cadence. 3–5 years of experience in VLSI/SOC design verification. System Verilog, UVM, and Verification tools expertise required.
Requirements
- Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field
- 3–5 years of experience in VLSI/SOC design verification
- Strong expertise in System Verilog, UVM, and Verification tools
Benefits
- We’re doing work that matters. Help us solve what others can’t.