At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsible for supporting integration / customization / post silicon bring up of CDNS DDR IP subsystems.
Requirements
- M.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)
- 7+ years of experience
- Sound knowledge of DDR4/5, LPDDR4/5 IP
- Hands on design/verification experience on DDR protocol
- Exposure to DDR Integration and Verification at SOC Level
- Exposure to Silicon Bring-up/Testing for DDR
- Hands on design/verification experience on AMBA based protocols like AXI, AHB, APB
- Experience on cadence tools
- Exposure to Lint/CDC, Synthesis, Static Timing Analysis review
- Exposure to all major IC implementation, design, and verification tools
- Willing to travel to customer sites worldwide
Benefits
- Generous Paid Time Off
- 401k Matching
- Retirement Plan
- Visa Sponsorship
- Four Day Work Week
- Generous Parental Leave
- Tuition Reimbursement
- Relocation Assistance