Senior Principal Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The ideal candidate will be energetic, innovative and enthusiastic about how to help customers solve their toughest verification problems using Cadence technology.

Requirements

• BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field
• 5+ years experience with SystemVerilog, VHDL, Verilog
• Verification skills such as UVM testbench architecture, development and debug
• Strong RTL and Testbench debug skills
• Experience in writing scripts (Perl, Python or Tcl)
• Strong software, HDL design and verification skills
• Ability to quickly analyze verification environments and design complexity
• Strong verbal and written communication skills
• Strong teamwork skills
• Ability to interact effectively with both external customers and R&D teams

Benefits

• Paid vacation and paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• Medical, dental and vision plan options