Senior Principal Software Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our R&D team building next-gen Accelerated Verification IP (AVIP) and Virtual Bridge solutions for high-performance IO and memory coherence.

Requirements

• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• Experience with PCIe and/or CXL design/verification, deep protocol-layer knowledge (LTSSM, DLL/TLP, flow control, ordering)
• Proficiency in Verilog RTL design and debug
• Experience with emulation/acceleration or hybrid (virtual + RTL) flows; solid debug skills (waveforms, checkers, coverage)

Benefits

• Paid vacation
• Paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• Medical, dental, and vision plan options