Ethernet ASIC Design Engineer

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies.

Requirements

• Design and implement advanced Ethernet protocols for next-generation Ethernet switch ASICs, focusing on RTL development.
• Develop microarchitecture specifications for Ethernet protocol blocks.
• Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and Security in Transmit and Receive pipelines using Verilog/System Verilog.
• Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
• Contribute to performance optimization and power-aware design strategies for Ethernet subsystems.

Benefits

• Medical, dental, and vision coverage
• Disability and life insurance
• Dependent care flexible spending account
• Accidental injury insurance
• Pet insurance
• Generous paid holidays
• 401(k) with company match
• Open Time Off (OTO)
• Sick time
• Bonding leave
• Pregnancy disability leave