PCIe ASIC Design Engineer

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. We are hiring a Senior ASIC Design Engineer to lead the design and integration of PCIe controllers into our next-generation SoCs.

Requirements

• Own end-to-end integration of PCIe IP into complex ASIC designs.
• Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
• Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
• Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability.
• Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams.
• Debug functional and performance issues at RTL, gate-level, and silicon.
• Ensure compliance with PCIe specifications and participate in interoperability testing where needed.
• Provide mentorship to junior engineers and help define PCIe subsystem development best practices.

Benefits

• Medical, dental, and vision coverage
• Disability and life insurance
• Dependent care flexible spending account
• Accidental injury insurance
• Pet insurance
• Generous paid holidays
• 401(k) with company match
• Open Time Off (OTO)
• Sick time
• Bonding leave
• Pregnancy disability leave