We are seeking an experienced Physical Design Engineer to join our team developing next-generation AI acceleration SoCs and chiplets at EdgeCortix.

Requirements

Drive and maintain RTL-to-GDSII flow, focusing on synthesis, STA, and design closure.
Strong Synthesis knowledge essential.
Able to conduct multiple experiments at Synthesis and take it to P&R and provide feedback to IP teams
Define floorplans and block partitioning strategies for hierarchical designs.
Coordinate with external vendors for backend P&R execution; review their outputs for quality and correctness.
Analyze timing paths and lead STA closure across PVT corners and operating modes.
Develop and optimize physical constraints (SDC, TCL) and run equivalence checks.
Placement analysis, congestion analysis, Clock Tree implementation experience needed
Evaluate standard cell libraries and implementation methodologies to improve PPA.
Implement low-power design strategies using UPF (Unified Power Format).
Review power grid planning and sign-off reports (IR-drop, EM).
Drive ECO implementation based on RTL changes or timing requirements.
Collaborate with internal RTL and architecture teams to improve logic and system-level PPA.
Participate in early feasibility studies and contribute to PPA projections.
Maintain and improve internal automation scripts and flows.

Benefits

We are seeking an experienced Physical Design Engineer to join our team developing next-generation AI acceleration SoCs and chiplets at EdgeCortix.

Drive and maintain RTL-to-GDSII flow, focusing on synthesis, STA, and design closure.
Strong Synthesis knowledge essential.
Able to conduct multiple experiments at Synthesis and take it to P&R and provide feedback to IP teams
Define floorplans and block partitioning strategies for hierarchical designs.
Coordinate with external vendors for backend P&R execution; review their outputs for quality and correctness.
Analyze timing paths and lead STA closure across PVT corners and operating modes.
Develop and optimize physical constraints (SDC, TCL) and run equivalence checks.
Placement analysis, congestion analysis, Clock Tree implementation experience needed
Evaluate standard cell libraries and implementation methodologies to improve PPA.
Implement low-power design strategies using UPF (Unified Power Format).
Review power grid planning and sign-off reports (IR-drop, EM).
Drive ECO implementation based on RTL changes or timing requirements.
Collaborate with internal RTL and architecture teams to improve logic and system-level PPA.
Participate in early feasibility studies and contribute to PPA projections.
Maintain and improve internal automation scripts and flows.