Design Verification Engineer | ASIC Verification Engineer (UVM/SystemVerilog)

We are looking for a Design Verification Engineer with experience in IP/Block/Subsystem verification, SystemVerilog, and UVM methodology.

Requirements

• 4–6 years in IP/Block/Subsystem verification
• Strong expertise in SystemVerilog and UVM methodology
• Experience building test plans, environments, and testbenches
• Strong RTL debugging, assertions, and coverage analysis
• Knowledge of AXI/AHB and protocols like DDR, PCIe, NVMe
• Experience in end-to-end verification from plan to signoff
• Exposure to mentoring and working in global teams
• Strong communication and problem-solving skills