ASIC Design Verification Engineer | UVM | Exp 8+ Years

Role Overview

Contribute to a multi-disciplined engineering team to design, verify, and develop ASIC and ASIC subsystems for Cisco platforms. Collaborate with designers, architects, and software teams to address and debug issues during post-silicon bring-up.

What You Will Do

Design, document, and develop ASIC subsystems for release in high volume and quality. Develop test plans and tests for qualifying design at block, cluster, and higher-level environments. Ensure complete verification coverage through implementation and review of code and functional coverage.

Why It Might Be a Fit

Proficient in ASIC verification using UVM/System Verilog. Experience building test benches from scratch, hands on experience with System Verilog constraints, structures, and classes. Scripting experience with Perl and/or Python.

Requirements

• Bachelor’s Degree with 7+ years of relevant ASIC design verification experience
• Masters Degree with 5+ years of relevant ASIC design verification experience
• Proficient in ASIC verification using UVM/System Verilog
• Proficient in verifying sophisticated blocks, clusters, and top-level for ASIC
• Experience building test benches from scratch, hands on experience with System Verilog constraints, structures, and classes
• Scripting experience with Perl and/or Python