ASIC Design Verification Engineer | 7+ Yrs | BLR

Role Overview

The Common Hardware Group (CHG) delivers silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams to ensure the successful verification of the ASIC throughout its lifecycle.

What You Will Do

Develop DV infrastructure, maintain and improve existing DV environments, develop test plans and tests, ensure complete verification coverage, and lead all aspects of the ASIC bring-up process.

Why It Might Be a Fit

You will contribute to developing Cisco’s progressive data center by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications.

Requirements

• Bachelor’s Degree or equivalent experience in EE, CE, or other related field
• 7+ years of related ASIC design verification experience
• Proficient in ASIC verification using UVM/System Verilog
• Proficient in verifying sophisticated blocks, clusters and top level for ASIC
• Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes