Senior ASIC Verification Engineer

Senior ASIC Verification Engineer will verify complex networking ASICs at both block level and full-chip level. This role involves creating testbenches using SystemVerilog and UVM, building high-quality verification environments, writing directed and constrained-random tests, debugging failures, and working closely with architecture, design, and emulation teams.

Requirements

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of experience in ASIC or SoC verification.
• Strong hands-on experience with SystemVerilog and UVM.
• Experience verifying networking ASICs (switching, routing, packet processing, or similar) is desired.
• Solid understanding of: Constrained-random verification, Directed and scenario-based testing, Coverage-driven methodologies, Assertions (SVA), Experience writing and optimizing C++ and/or SystemC reference models, Experience with emulation environments and post-silicon debug, Familiarity with EDA tools for simulation, debug, coverage, waveform analysis, and formal checks.

Benefits

• Health & Wellbeing
• Personal & Professional Development
• Unconditional Inclusion