Hewlett Packard Enterprise is seeking a Senior ASIC Verification Engineer to verify complex networking ASICs at both block level and full-chip level. The role involves creating testbenches using SystemVerilog and UVM, building high-quality verification environments, and working closely with architecture, design, and emulation teams.
Requirements
- Bachelorâs, Masterâs, or PhD in Electrical Engineering, Computer Engineering, or related field.
- 8+ years of experience in ASIC or SoC verification.
- Strong hands-on experience with SystemVerilog and UVM.
- Experience verifying networking ASICs (switching, routing, packet processing, or similar) is desired.
- Solid understanding of constrained-random verification, directed and scenario-based testing, coverage-driven methodologies, and assertions (SVA).
- Experience writing and optimizing C++ and/or SystemC reference models.
- Experience with emulation environments and post-silicon debug.
- Familiarity with EDA tools for simulation, debug, coverage, waveform analysis, and formal checks.
- Strong problem-solving skills and ability to debug complex design/testbench interactions.
- Excellent communication and teamwork skills.
Benefits
- Health & Wellbeing
- Personal & Professional Development
- Unconditional Inclusion