Design Verification Lead

Design Verification Lead at InnoPhase IoT. Responsible for constructing SoC level test benches, developing verification plans, and verifying SoC using advanced verification methodologies.

Requirements

• BSEE or MSEE
• 7+ years of experience in RTL design using Verilog, SystemVerilog
• Understanding of Digital Signal Processing theory, and mapping to design
• Experience in WiFi Physical Layer, and/or other Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and/or other Physical layer (Ethernet) technologies

Benefits

• Dynamic and functionally diverse team with opportunities for gaining exposure to modeling (TLM), HW emulation/acceleration, and SW driven verification
• Opportunities for growth and meaningful contributions
• Recognition and appreciation for motivated employees