Lead SoC Logic Design Engineer

Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.

Requirements

• BSEE/CE minimum, MS preferred
• 10 plus years' experience in IC/SoC Design and Micro Architecture
• Experience in all phases of logic development lifecycle from high-level specification to tape-out and production
• Expertise in one or more of the following domains X86 Server Micro Architecture Reset and Clocking Power Management DFX - Scan, JTAG, VISA, Integration etc.
• Experience in DFD (Design for Debug) and Coherent Fabric
• Excellent communication and documentation skill
• Must be skilled to influence in heavily matrixed environment
• Capable to operate in ambiguity where roles may not be clearly defined or teams across multiple/functions and IP/SOC must be pulled together