Senior Logic Design Verification Engineer

As a Senior Logic Design Verification Engineer, you will work on defining and developing verification testbench and building RTL models for verification, validating and verifying the functionality of new architectural features, and implementing corrective measures for failing RTL tests.

Requirements

• Possess a Bachelor's, a Master's degree or a Ph.D. in Electronics Engineering, Computer Engineering, or equivalent
• At least 8 years of relevant working experience in design verification with UVM and System Verilog
• Familiarize with UVM Verification Components and Bus-functional Models (BFM)
• Strong in UVM application, analysis, debugging skills, and creative in problem solving

Benefits

• Competitive salary
• Benefits package
• Opportunities for career growth and development