Marvell is seeking a Senior Engineer, Physical Design to work on the physical design and methodology for future designs of high-performance processor chips in a leading-edge CMOS process technology. The role will involve working with a global team on complex chip design and methodology, with a focus on block-level PNR for advanced CMOS process nodes.
Requirements
- Bachelor’s, master’s, or PhD degree in electrical engineering, computer engineering, or a related field
- 3+ years of experience in physical design with a focus on block-level PNR for advanced CMOS process nodes
- Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus and Synopsys IC Compiler and Fusion Compiler
- Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail
- Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality)
- Enjoy learning by doing the work and having access to guides and a mentor
- Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before
Benefits
- Competitive compensation
- Great benefits
- Shared collaboration, transparency, and inclusivity
- Access to guides and a mentor