Senior Physical Design Engineer

Micron Technology is seeking a Senior Physical Design Engineer to own end-to-end physical implementation for SoC blocks and/or top-level designs, leading timing closure and collaborating with design, integration, and system teams. The ideal candidate will have 4-8 years of experience in physical design implementation for complex SoC or large-scale digital blocks, strong experience in block-level timing analysis and closure, and proficiency with industry-standard place-and-route tools.

Requirements

• 4–8 years of hands-on experience in physical design implementation for complex SoC or large-scale digital blocks
• Strong experience in block-level timing analysis and closure, including setup/hold closure across multi-mode, multi-corner (MMMC) scenarios
• Proficiency with industry-standard place-and-route tools such as Cadence Innovus and/or Synopsys IC Compiler II
• Hands-on expertise in physical verification and signoff closure, including DRC, LVS, antenna, and related foundry checks
• Strong understanding of power integrity and reliability analysis, including IR drop, electromigration (EM), noise, coupling, and crosstalk
• Demonstrated ability to analyze and close IR/EM issues at the block level, working closely with power, signoff, and technology teams
• Solid foundation in digital design fundamentals, including digital electronics, microprocessors, and computer architecture
• Experience in bringing to bear automation and scripting (e.g., Tcl, Python, or equivalent) to improve physical develop efficiency, quality, and turnaround time
• Exposure to AI-assisted tools and workflows, including timely engineering or analysis supported by AI
• Proven ability to mentor and guide less-experienced engineers, contributing to technical skill development, build reviews, and sharing effective approaches within the team