Senior Principal Analog Design Engineer – Power & Clock IP

onsemi is seeking a Senior Principal Analog Design Engineer to contribute to the development of power management and clocking analog IP blocks for Treo-based SoC platforms. The role will involve designing, simulating, and verifying power management IP, including LDOs, DC/DC converters, and charge pumps, as well as clocking circuits such as PLLs, DLLs, oscillators, and clock distribution networks. The ideal candidate will have experience in industry-standard schematic capture and SPICE/AMS simulation tools, and will be able to apply scripting, automation, or data-driven techniques to improve design productivity and robustness.

Requirements

• Bachelor's degree in Electrical Engineering or related field
• 10+ years of experience in analog design engineering
• Experience with industry-standard schematic capture and SPICE/AMS simulation tools
• Knowledge of power management and clocking circuit design
• Experience with scripting, automation, or data-driven techniques to improve design productivity and robustness