Principal Static Timing Analysis Engineer

Silicon Labs is seeking a Principal Static Timing Analysis Engineer to develop timing constraints and timing closure signoff of low power Wireless SoCs and IP systems. The role involves collaboration with designers, analysis of timing reports, and driving rapid timing closure. The position requires a strong understanding of timing closure flow and methodology, as well as experience with static timing tools and scripting languages.

Requirements

• Develop timing constraints at both the IP and SoC level
• Improve or evolve existing static timing analysis flows and methodologies
• Develop required timing signoff criteria
• Analyze timing reports using scripting techniques
• Collaborate with a global design team to resolve complex static timing issues
• Collaborate with a multi-functional team to drive timing closure for mixed-signal IP integration

Benefits

• Great medical, dental, and vision plans
• Highly competitive salary
• 401k plan with match and Roth plan option
• Equity rewards (RSUs)
• Life/AD&D and disability coverage
• Flexible spending accounts
• Adoption assistance
• Back-Up childcare
• Additional benefit options
• Flexible PTO schedule
• 3 paid volunteer days per year
• Charitable contribution match
• Tuition reimbursement
• Free downtown parking
• Onsite gym
• Monthly wellness offerings
• Free snacks
• Monthly company updates with our CEO