ASIC Digital Design Engineer, Staff

Synopsys is seeking an ASIC Digital Design Engineer, Staff to join their team in Bengaluru, India. The ideal candidate will have 5-10 years of experience in IP and SoC verification, with a strong background in verification methodologies and tools such as Synopsys VCS, Verdi, and VIPs. The role will involve applying AI techniques to accelerate design verification, implementing reference and unified verification flows, and building robust verification infrastructures. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. Synopsys offers a comprehensive range of health, wellness, and financial benefits.

Requirements

• Minimum 5 to 10 years of hands-on experience in IP/SoC verification
• Good understanding of Agentic AI technologies specifically Cursor and/or VS Code co-pilot
• Familiarity with Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs
• Demonstrated ability to validate verification flows and infrastructure for complex digital designs
• Solid programming and scripting skills (SystemVerilog, UVM, Tcl, Python or similar languages)
• Bachelor’s degree in electronics, electrical, or computer engineering (advanced degrees a plus)

Benefits

• Comprehensive health, wellness, and financial benefits
• Monetary and non-monetary rewards