ASIC Digital Design Engineer, Staff

We are seeking a highly experienced ASIC Digital Design Engineer to join our team. As a Staff Engineer, you will be responsible for implementing reference and unified verification flows, building robust verification infrastructures, and leading and mentoring junior engineers. You will work closely with global engineering teams to define and document best-in-class verification methodologies and standards. You will also drive technical initiatives, manage high-impact assignments, and collaborate with tool development teams to influence product evolution and optimize verification workflows.

Requirements

• Minimum 5 to 10 years of hands-on experience in IP/SoC verification
• Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs
• Demonstrated ability to architect and implement verification flows and infrastructure for complex digital designs
• Solid programming and scripting skills (SystemVerilog, UVM, Tcl, Python or similar languages)
• Bachelor’s degree in electronics, electrical, or computer engineering (advanced degrees a plus)
• Experience with multi-tasking and managing technical projects independently
• Ability to document, communicate, and propagate technical methodologies across global teams

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards include both monetary and non-monetary offerings