ASIC Digital Design, Manager

We are seeking a passionate engineering leader with a strong foundation in digital and mixed-signal design to manage our ASIC digital design team. The ideal candidate will have at least five years of industry experience and a background in ASIC design and verification, with expertise in Verilog or VHDL.

Requirements

• MSEE (preferred) or equivalent with a minimum of 5 years’ experience in digital design and verification
• Proven proficiency in Verilog or VHDL for ASIC development
• Experience with code quality metrics and coverage-driven verification methodologies
• In-depth knowledge of high-speed digital and mixed-signal design, asynchronous clock crossings, and DFT methodologies
• Strong understanding of CDC, synthesis, and power optimization techniques
• Hands-on experience with simulation tools and collaborative debugging in verification environments
• Ability to develop system-level specifications for complex digital and analog systems

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards include both monetary and non-monetary offerings