ASIC Digital Design, Senior Staff Engineer-14867
SynopsysOttawa, Ontario, Canada
Posted January 23, 2026
Full Time
About the Company
Synopsys is a global leader in engineering solutions that span the entire silicon‑to‑system lifecycle, empowering customers to accelerate the development of AI‑powered products. The company delivers cutting‑edge silicon design, semiconductor IP, electronic design automation (EDA), and simulation and analysis tools, complemented by professional design services. Synopsys distinguishes itself through deep industry partnerships that enhance R&D productivity and unlock innovative capabilities across technology sectors. Its commitment to software quality and security further ensures reliable, high‑performance solutions for complex electronic systems.
Job Description
We are seeking a Senior Staff Engineer to develop and deliver RTL designs for High Bandwidth Memory (HBM) PHY IP. The ideal candidate will have 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.
Requirements
- 7-10 years of hands-on experience in RTL design
- Expertise in SystemVerilog and Verilog for RTL development
- Strong background in high-speed design, timing closure, and low power design techniques and strategies
- Experience with the entire ASIC and IP development flow, including DFT/DFM, and debugging complex hardware issues
- Proficiency in automating tasks using scripting languages (e.g., Python, Perl, TCL)
- Familiarity with modeling analog and mixed-signal circuits and understanding of physical implementation challenges
- Ability to write clear, detailed specification documents and provide technical support to cross-functional teams
Benefits
- Comprehensive range of health, wellness, and financial benefits
- Monetary and non-monetary offerings